I know ᴀꜱɪᴄs are more efficient but I’d like to make the customizations myself and be able to reconfigure to other mining algorithms as the target cryptocurrency uses sha256 for proof of work but in a way that makes Bitcoin miners incompatible (sha256 one time from a single 32bytes input instead of twice).

The problem is all the Verilog or ᴠʜᴅʟ source code I found seems to be purely iterative or focuses only on the characteristics of the Bitcoin block to perform some sha256 precomputations. Bitmain’s antimers on the other end, likely fully leverage the possibilities from the ability to use netlists to get the highest throughput per logic blocks. In order to reach this, this means carry‑save adders ; factor 2 or maybe 4 unfolding ; architectural folding ; not only 1 but double pipelining ; shift registers design for shrinking number of ʟᴜᴛ used ; thermal optimization ; and all of this while shrinking the room usage of 1 sha256 unit in order to have the maximum units possible on a single chip clocked at the max ᴛᴅᴘ.

But I failed to find the source code of such an advanced design and I lack the knowledge to write such advanced code. This paper if not a hoax, seems to be what I need but I’m failing to contact any of the authors to get more details.


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