As mentioned, emulation refers to implementing an HDL design on a set of FPGAs.
If you want to truly simulate and verify at the transistor level, you'll need more than just a simulator as there is timing issues involved. You'll also need to place and route the transistors, and take the delay data from the layout and annotate it back into the original functional simulation.
These tools, at basic level, cost in excess of $750,000 dollars. I'd suggest instead of an ASIC, you use the following free FPGA tools:
Once you have the FPGA working, you can then buy the tools necessary to complete the ASIC. This should cost less than $2000 total. You can use service companies to build the ASIC for you:
which will probably be cheaper than doing it yourself the first or fifth time.
If you are certain that you want to do transistor level simulation, VHDL will not work for you. Verilog contains transistor level elements such as cmos, nmos, tranif, etc that will allow transistor level simulation. Aldec and Mentor Graphics offer the lowest cost simulators that would approved for most ASIC foundries, under $5000.
Mentor (questa is more expensive than modelsim):
Review this analysis for ASIC vs FPGA for startup:
and if you do decide to go ASIC, try and go through a foundry that will allow you to buy a portion of the silicon wafer instead of the whole wafer. They will provide you files that will allow you to create the timing sdf files needed for simulating your transistor level circuits.