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I have created a nifty reconfigurable logic array using Chisel and find myself without means to test the resulting Verilog. I can see that the generated Verilog is likely correct by comparing the Verilog output with Verilog from a version of the Chisel source where the connections that could cause combinational feedback have been eliminated.

Does anyone know of any open source tools that may be up to the task of simulating this circuit?

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You have a couple of options:

  • If your main concern is speed and you don't care about testbench features, have a look at Verilator, which supports just the synthesizable subset of Verilog (up to the "more important features of Verilog 2005).
  • If you need a few more testbench features, try GPL Cver, but keep in mind that it only supports Verilog 1995 (with some Verilog-2001 features).
  • If you need better Verilog support, I'd suggest Icarus Verilog, which aims to support the full Verilog-2005 standard.

My personal choice would be Icarus Verilog as I prefer to use a richer subset of the Verilog HDL, but if you are mainly looking for interfacing your generated Verilog with existing C/C++, Verilator might your option.

Also I wasn't able to find any information about the Verilog subset generated by Chisel, so that could further limit your options.

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  • Those guys use Synoptics tools to process their Verilog, so I expect their Verilog conforms to the features and limitations of that toolset. – Mykland Jan 12 '16 at 20:54
  • Synopsys, that is. – Mykland Jan 12 '16 at 20:55

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