I have created a nifty reconfigurable logic array using Chisel and find myself without means to test the resulting Verilog. I can see that the generated Verilog is likely correct by comparing the Verilog output with Verilog from a version of the Chisel source where the connections that could cause combinational feedback have been eliminated.
Does anyone know of any open source tools that may be up to the task of simulating this circuit?