Software to simulate ASIC chip logic

Question

Which software can be used to emulate a ASIC's gate-arrays (matrix of transistors?) in order to test predefined logic cells and custom interconnections before ordering a final device?

Either on PC or Mac.

Could be similar to software for simulating electrical circuits, but I don't know if that supports ASIC devices.

No specific price tag, but it should be reasonable.

Answer 1

Are you really developing an ASIC? If so, you should have access to industrial strength simulators such as VCS and Model Sim.

If you aren't, use the simulator that comes with your FPGA vendor's tools. Xilinx, Altera, and I think Lattice have them. They have free licenses for their small to medium devices.

Also "emulator" often refers to "a bunch of FPGAs pretending to be a ASIC before we commit to tape-out of it" rather than software-only simulation. Read more on Wikipedia.

Answer 2

As mentioned, emulation refers to implementing an HDL design on a set of FPGAs.

If you want to truly simulate and verify at the transistor level, you'll need more than just a simulator as there is timing issues involved. You'll also need to place and route the transistors, and take the delay data from the layout and annotate it back into the original functional simulation.

These tools, at basic level, cost in excess of $750,000 dollars. I'd suggest instead of an ASIC, you use the following free FPGA tools:

http://dl.altera.com/?edition=lite

https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html

Once you have the FPGA working, you can then buy the tools necessary to complete the ASIC. This should cost less than $2000 total. You can use service companies to build the ASIC for you:

http://fidus.com/

https://www.aligned.com/

https://www.esilicon.com/company/

which will probably be cheaper than doing it yourself the first or fifth time.

If you are certain that you want to do transistor level simulation, VHDL will not work for you. Verilog contains transistor level elements such as cmos, nmos, tranif, etc that will allow transistor level simulation. Aldec and Mentor Graphics offer the lowest cost simulators that would approved for most ASIC foundries, under $5000.

Aldec: https://www.aldec.com/en/products/functional_verification/riviera-pro

Mentor (questa is more expensive than modelsim): https://www.mentor.com/products/fv/questa/

Review this analysis for ASIC vs FPGA for startup:

https://spectrum.ieee.org/tech-talk/computing/hardware/lowbudget-chip-design-how-hard-is-it

and if you do decide to go ASIC, try and go through a foundry that will allow you to buy a portion of the silicon wafer instead of the whole wafer. They will provide you files that will allow you to create the timing sdf files needed for simulating your transistor level circuits.

Answer 3

As far as I understand, ASIC gate array logic can be written in a hardware description language (HDL) which is kind of computer language specially designed to describe the structure and behavior of electronic circuits.

So to perform the logic simulation, you just need a software which can simulate/debug the HDL code either for analog circuit design, digital circuit design or printed circuit board design.

There are variety of HDL implementation design languages, so for more details, please check examples of HDLs at Wikipedia. Depending on such implementation, the code is converted into VHDL (VHSIC Hardware Description Language).

VHDL is frequently used for two different goals: simulation of electronic designs and synthesis of such designs. Synthesis is a process where a VHDL is compiled and mapped into an implementation technology such as an FPGA or an ASIC.

A simple AND gate in VHDL would look something like^wiki:

-- (this is a VHDL comment)

-- import std_logic from the IEEE library
library IEEE;
use IEEE.std_logic_1164.all;

-- this is the entity
entity ANDGATE is
  port ( 
    I1 : in std_logic;
    I2 : in std_logic;
    O  : out std_logic);
end entity ANDGATE;

-- this is the architecture
architecture RTL of ANDGATE is
begin
  O <= I1 and I2;
end architecture RTL;